Complementary metal-oxide-semiconductor (MOS) devices have been the basic logic building blocks in the formation of integrated circuits. In traditional IC processes, gate electrodes are typically formed of polysilicon. One of the reasons for polysilicon's wide use is that the work function of polysilicon gate electrodes can be changed easily by doping with different impurities. However, polysilicon has depletion problems, and hence metal gate electrodes were introduced, particularly for MOS device in core regions, to avoid the poly depletion phenomenon.
With the adoption of metal gates, naturally, core MOS devices, input/output (I/O) MOS devices, and static random access memory (SRAM) MOS devices may all have metal gates, so that they can be manufactured simultaneously to reduce the manufacturing cost. In addition, other devices manufactured simultaneously with the MOS devices, such as resistors, MOS capacitors, and the like, will also be formed of metals. This significantly changes the electrical properties of these devices. The standard libraries built in the past decades for simulating the behavior of these devices thus have to be rebuilt, which is highly costly and time consuming.
In addition, I/O MOS devices typically prefer thick silicon oxides as the gate dielectrics. Therefore, integration schemes have been developed to integrate I/O MOS devices having polysilicon gates and core MOS devices having metal gates on a same chip. However, the manufacturing schemes for forming such structures are often complicated, and the manufacturing cost is high.
Accordingly, what is needed in the art is an integrated manufacturing scheme to satisfy both the requirements of the core MOS devices and I/O MOS devices, and to address the standard library issues.